Registered user since Mon 4 Jul 2016
Name: Hironori Kasahara
Bio: Hironori Kasahara has served as a chair or member of 225 society and government committees, including a member of the IEEE CS Board of Governors; chair of CS Multicore STC and CS Japan chapter; associate editor of IEEE Transactions on Computers; vice PC chair of the ACM 1996 ENIAC 50th Anniversary International Conference on Supercomputing; general chair of LCPC; PC member of SC, PACT, PPoPP, and ASPLOS; board member of IEEE Tokyo section; and member of the Earth Simulator committee.
Kasahara received a PhD in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004.
He was a visiting scholar at University of California, Berkeley and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D.
He received the CS Golden Core Member Award, IFAC World Congress Young Author Prize, IPSJ Fellow and Sakai Special Research Award, and the Japanese Minister’s Science and Technology Prize.
Kasahara led Japanese national projects on parallelizing compilers and embedded multicores, and has presented 210 papers, 132 invited talks, and 27 patents. His research has been introduced in 520 newspaper and Web articles.
Affiliation: Waseda University, Japan
Personal website: http://www.kasahara.cs.waseda.ac.jp/kasahara.html.en
Research interests: Parallelizing Compiler, Multicore, Power Reduction, Locality Optimization, Vector Accelerator
|SEPS 2016||Author of Reducing Parallelizing Compilation Time by Removing Redundant Analysis within the SEPS-track|
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