Reducing Parallelizing Compilation Time by Removing Redundant Analysis
Parallelizing compilers equipped with powerful compiler optimizations are essential tools to fully exploit performance from today's computer systems. These optimizations are supported by both highly sophisticated program analysis techniques and aggressive program restructuring techniques. However, the compilation time for such powerful compilers becomes larger and larger for real commercial application due to these strong program analysis techniques. In this paper, we propose a compilation time reduction technique for parallelizing compilers. The basic idea of the proposed technique is based on an observation that parallelizing compilers applies multiple program analysis passes and restructuring passes to a source program but all program analysis passes do not have to be applied to the whole source program. Thus, there is an opportunity for compilation time reduction by removing redundant program analysis. We describe the removing redundant program analysis techniques considering the inter-procedural propagation of annalysis update information in this paper. We implement the proposed technique into OSCAR automatically multigrain parallelizing compiler. We then evaluate the proposed technique by using three proprietary large scale programs. The proposed technique can remove 37.7% of program analysis time on average for basic analysis includes def-use analysis and dependence calculation, and 51.7% for pointer analysis, respectively.
Tue 1 NovDisplayed time zone: Amsterdam, Berlin, Bern, Rome, Stockholm, Vienna change
10:30 - 12:10 | |||
10:30 25mTalk | Reducing Parallelizing Compilation Time by Removing Redundant Analysis SEPS Jixin Han Waseda University, Japan, Rina Fujino Waseda University, Japan, Ryota Tamura Waseda University, Japan, Mamoru Shimaoka Waseda University, Japan, Hiroki Mikami Waseda University, Japan, Moriyuki Takamura OSCAR TECHNOLOGY, Japan, Sachio Kamiya OSCAR TECHNOLOGY, Japan, Kazuhiko Suzuki OSCAR TECHNOLOGY, Japan, Takahiro Miyajima OSCAR TECHNOLOGY, Japan, Keiji Kimura Waseda University, Hironori Kasahara Waseda University, Japan DOI | ||
10:55 25mTalk | A Divide-and-Conquer Parallel Pattern Implementation for Multicores SEPS Marco Danelutto University of Pisa, Italy, Tiziano De Matteis University of Pisa, Italy, Gabriele Mencagli University of Pisa, Italy, Massimo Torquati University of Pisa, Italy DOI | ||
11:20 25mTalk | Parallel Evaluation of a DSP Algorithm using Julia SEPS Peter Kourzanov NXP, Netherlands DOI | ||
11:45 25mTalk | Exhaustive Analysis of Thread-Level Speculation SEPS Clark Verbrugge McGill University, Canada, Christopher J. F. Pickett McGill University, Canada, Alexander Krolik McGill University, Canada, Allan Kielstra IBM, Canada DOI |