Blogs (9) >>
Sun 30 October - Fri 4 November 2016 Amsterdam, Netherlands
Tue 1 Nov 2016 11:20 - 11:45 at St Gallen - Session 2 Chair(s): Tamer Dallou

Rapid pace of innovation in industrial research labs requires fast algorithm evaluation cycles. The use of multi-core hardware and distributed clusters is essential to achieve reasonable turnaround times for high-load simulations. Julia’s support for these as well as its pervasive multiple dispatch make it very attractive for high-performance technical computing.

Our experiments in speeding up a Digital Signal Processing (DSP) Intellectual Property (IP) model simulation for a Wireless LAN (WLAN) product confirm this. We augment standard SystemC High-Level Synthesis (HLS) tool-flow by an interactive worksheet supporting performance visualization and rapid design space exploration cycles.

Tue 1 Nov
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10:30 - 12:10: SEPS - Session 2 at St Gallen
Chair(s): Tamer DallouLG Electronics San Jose Lab
seps201610:30 - 10:55
Jixin HanWaseda University, Japan, Rina FujinoWaseda University, Japan, Ryota TamuraWaseda University, Japan, Mamoru ShimaokaWaseda University, Japan, Hiroki MikamiWaseda University, Japan, Moriyuki TakamuraOSCAR TECHNOLOGY, Japan, Sachio KamiyaOSCAR TECHNOLOGY, Japan, Kazuhiko SuzukiOSCAR TECHNOLOGY, Japan, Takahiro MiyajimaOSCAR TECHNOLOGY, Japan, Keiji Kimura Waseda University, Hironori KasaharaWaseda University, Japan
seps201610:55 - 11:20
Marco DaneluttoUniversity of Pisa, Italy, Tiziano De MatteisUniversity of Pisa, Italy, Gabriele MencagliUniversity of Pisa, Italy, Massimo TorquatiUniversity of Pisa, Italy
seps201611:20 - 11:45
Peter KourzanovNXP, Netherlands
seps201611:45 - 12:10
Clark VerbruggeMcGill University, Canada, Christopher J. F. PickettMcGill University, Canada, Alexander KrolikMcGill University, Canada, Allan KielstraIBM, Canada